Answered Essay: Frequency(%) 30 25 40 Cycles Instruction Type Arithmetic and logical Load and Store Branches Floating Point (FP) 3

You have the following characteristics, as shown in the table below, on your company’s processor for a certain benchmark, which runs at 400 MHz:

Frequency(%) 30 25 40 Cycles Instruction Type Arithmetic and logical Load and Store Branches Floating Point (FP) 3

You are asked to consider a cheaper, lower‐performance version of this processor, by removing some of the FP hardware to reduce the die size. The wafer has a diameter of 10 cm, costs $1,000, and has a defect rate of 2/(cm2 ). This wafer has a 75% yield. The current chip has a die size of 12 mm2 . The new chip becomes 10 mm2 , and FP instructions will now take 13 cycles to execute.

a) [10] What are the old and new CPI (Cycles Per Instructions) and MIPS (Million Instructions Per Second) ratings running this benchmark?

b) [10] What are the old and new die yields? What are the old and new costs per (working) processor? Please comment on the overall effect of the proposed hardware change on the cost and the performance of the processor.

c) [10] What would be the theoretical limit of the best possible overall speedup that we could ever get by only improving the FP unit, and what would be the CPI and MIPS ratings of this new processor?

Frequency(%) 30 25 40 Cycles Instruction Type Arithmetic and logical Load and Store Branches Floating Point (FP) 3

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