The circuit shown uses compound superbeta transistors (also called the Sziklai topology).
Assume PL(max) = 20W driving an RL = 4.5? load. Also assume sufficient symmetry in the pull and pull-down transistor so that 1 = 2 = 25 and 3 = 4 = 40. Assume that R3, R4 divert 25% of the current away from the base nodes of the Q1, Q2 drive transistors (R3 , R4 increase the ON-OFF speed).
a)VL(max) and resulting ? IS(max) ?
b) S for each compound transistor pair.
c)If Ibias = 4.5mA and the current IR through R1 and R2 is elected to be 0.25mA what values result for quiescent levels IQ and PDQ assuming VS = VL(max)?
d)If the power supply is VS = ±15V what is VL(worst) and PD(worst, tot) for the circuit ?
e) For part (d) what is the PS at VL = VL(max) and the efficiency?
*ゆく +VE R3 bl36 01 03 VL 05 R1 04 Vin R4